Achieving Design Closure Through Delay Relaxation Parameter

Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of design closure from a high level point of view. A new metric called delay relaxation parameter (DRP) for RTL designs is proposed. DRP essentially captures the degree of delay relaxation that the design can tolerate without violating the clock constraint. This metric when optimized results in quicker design flow. Algorithms to optimize DRP are formulated and their optimality are investigated. Experimental results are conducted using a state of the art design flow with Synopsys Design Compiler followed by Cadence Place and Route. Our approach of optimizing DRP resulted in lesser design iterations and faster design closure as compared to designs generated through Synopsys Behavioral Compiler and a representative academic design flow. For most benchmarks, our approach resulted in faster clock frequency when compared with other approaches. Even when both approaches met the clock constraint, our approach was better in design quality (placement area, routing wirelength, number of vias). The overall design time was faster. These comparisons were made at layout level, therefore they represent real improvements.